A Dual Rail Circuit Technique to Tolerate Routing Imbalances
نویسندگان
چکیده
Dual Rail Precharge (DRP) circuits, which are theoretically secure against differential power analysis attacks, suffer from an implementation problem: balancing routing capacitance of differential signals. To solve this, four proposals have been put forward: DWDDL [18], FatWire [19], Backend Duplication [4] and Three Phase Dual Rail [2]. Of these, three of them (DWDDL, FatWire, Backend Duplication) alter the routing mechanism of Standard Place and Route tools, which introduces an additional step and is not desired. The other proposal, Three Phase Dual Rail, introduces a third phase which reduces the systems performance. In this paper we propose a new countermeasure, Path Switching, to address the routing problem in DRP circuits. From SPICE simulations we show that our proposal does not reveal the secret key for up to 300,000 traces, an increase of 75 times over normal Dual Rail circuits and 3000 times over normal single rail circuits.
منابع مشابه
Masking and Dual-Rail Logic Don't Add Up
Masked logic styles use a random mask bit to de-correlate the power consumption of the circuit from the state of the algorithm. The effect of the random mask bit is that the circuit switches between two complementary states with a different power profile. Earlier work has shown that the mask-bit value can be estimated from the power consumption profile, and that masked logic remains susceptible...
متن کاملMulti-Threshold Dual-Spacer Dual-Rail Delay-Insensitive Logic (MTD3L): A Low Overhead Secure IC Design Methodology
As portable devices become more ubiquitous, data security in these devices is becoming increasingly important. Traditional circuit design techniques leave otherwise secure systems vulnerable due to the characteristics of the hardware implementation, rather than weaknesses in the security algorithms. These characteristics, called side-channels, are exploitable because they can be measured and co...
متن کاملEvaluating the Duplication of Dual-Rail Precharge Logics on FPGAs
Power-equalization schemes for digital circuits aim to harden cryptographic designs against power analysis attacks. With respect to dual-rail logics most of these schemes have originally been designed for ASIC platforms, but much efforts have been spent to map them to FPGAs as well. A particular challenge is here to apply those schemes to the predefined logic structures of FPGAs (i.e., slices, ...
متن کاملDivided Backend Duplication Methodology for Balanced Dual Rail Routing
Dual Rail Precharge circuits offer an effective way to address Differential Power Analysis Attacks, provided routing of differential signals is fully balanced. Fat Wire [1] and Backend Duplication [2] methods address this problem. However they do not consider the effect of coupling capacitance on adjacent differential signals. In this paper we propose a new method, Divided Backend Duplication, ...
متن کاملMasked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints
During the last years, several logic styles that counteract side-channel attacks have been proposed. They all have in common that their level of resistance heavily depends on implementation constraints that are costly to satisfy. For example, the capacitive load of complementary wires in an integrated circuit may need to be balanced. This article describes a novel side-channel analysis resistan...
متن کامل